Processors being developed in recent years have a largely increased operation speed, and the quantity of data being processed within unit time is constantly increased. Thus, either the transmission of data between a computer and peripheral equipment, or various applications of integrated circuit (IC) products must rely on an interface circuit capable of transmitting and receiving very large amount of data. While an optical fiber may be used to transmit data over a long distance from a few decades to a few hundreds of kilometers, it is impractical to use the optical fiber to transmit data within a few meters or between different on-chip buses on a circuit board. Therefore, cables or links on a circuit board are used to receive and transmit data. In conventional techniques, the bandwidth and transmission rate are increased by increasing the number of links. However, due to limited mounting area on the circuit board, and the demands for low power consumption, reduced production cost, and simplified production and assembling procedures, it is necessary to develop a more efficient interface design.
A low voltage differential signal (LVDS) has been widely employed on a video interface between a panel and an image control IC of a liquid crystal display (LCD). In the beginning, LVDS is developed to replace the high-power emitter-coupled logic (ECL) linear driving technique. By way of reducing power, the technique of LVDS enhances the limited characteristics of ECL and may be powered by a common power supply, highly integrated, and compatible with low-cost IC package.
LVDS is a physical layer data interface standard defined by ANSI/TIA/EIA-644 and IEEE 1596.3 standard specifications, and is also widely referred to as RS-644. This standard only defines the electric characteristics of driver output and receiver input, and does not include definition regarding the function, protocol, and cable thereof. The LVDS has been widely employed in communication and display interfaces to replace many traditional interfaces, such as RS-422, PECL (positive emitter coupling logic), and LV-PECL (low-voltage positive emitter-coupled logic). With the differential characteristic, the LVDS is superior to other interfaces in that (1) it may be used in an environment using low-voltage power supply, (2) it produces signals of low noise, (3) it has high anti-noise ability, (4) it has powerful signal transmitting ability, and (5) it may be easily integrated into a system chip.
Following the tendency of low weight and compactness, all kinds of electronic apparatus, from the circuit board to the bus for a display, must be produced slimmer and slimmer while providing higher transmission rate. An LVDS chipset is able to overcome this problem. For a circuit board with the LVDS chipset, some normally necessary resistors and capacitors may be canceled now to reduce the cost and required space of the circuit board.
While the conventional LVDS has the above-mentioned advantages, it also has some shortcomings in design that are difficult to break through up to date.
An LVDS connecting port consists of a clock differential pair and multiple data differential pairs. In each clock cycle, every data channel transmits 7 bits of data. For the receiver to correctly receive data, the edge of the clock must be aligned with the data bit stream in every data channel. FIG. 1 shows the sequences of LVDS clock and data.
In a common design for the conventional LVDS receiver, a phase locked loop (PLL) or a delay locked loop (DLL) is used to produce seven (7) phase clock signals, and each of the 7 phase clocks is used to retrieve corresponding data bits from the data stream. The edges of these 7 phase clock signals must be aligned with the corresponding data bits. FIG. 2 shows the configuration of a conventional LVDS receiver.
The problem in the existing LVDS receivers is that the clock and data signal channels have different delay times due to influences from many factors. Different factors, such as the number, the type, the manufacturing process, and the voltage variation of electronic elements on every channel, would result in differences in time sequence between each pair of corresponding clock and data. This tends to cause sampling errors to adversely affect the signal transmission quality. And, such adverse influence becomes significant with the increased data transmission rate.
To overcome the large quantity of sampling errors at the increased data transmission rate, it is necessary for the existing LVDS receiver to adjust the circuit layout against the different number, type, manufacturing process, and voltage variation of electronic elements between the clock and the data channels, so as to increase the data transmission rate and the signal transmission quality at the same time. However, it would take the manufacturer a large amount of time and efforts to do so.
That is, it is very difficult to increase the data transmission rate and the signal transmission quality at the same time under the existing LVDS receiver configuration.
It is therefore tried by the inventor to develop a low voltage differential signal receiving device to overcome the above-mentioned problem.